Consumer demand for increased mobility, wireless connectivity and advanced features have paved the way for a variety of new products including advanced mobile handsets, PDAs (Personal Digital Assistants), digital cameras and camcorders, portable music players and many other such devices. Silicon-based solutions driving these products are more highly integrated than ever before, as advancements in process technology have resulting in the delivery of System-on-a-Chip (SoC) solutions that are smaller, faster and increasingly inexpensive. These trends, along with a broad range of emerging end equipment, require a large diversity of new IC package types to meet specific applications or markets. Increased device complexity can generate an explosion of new creative and disruptive technology packaging solutions and in some markets and applications packaging technology is a key differentiator when making purchasing decisions.
Small Computer System Interface (SCSI), a parallel interface standard for attaching peripheral devices to computers has achieved a remarkable 320 Mbps data rate. Many new transmission technologies such as Ethernet, Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), and Fiber Channel (FC) have bit rates in excess of 5 Gbps. A typical channel in all of the mentioned protocols contains Signal Source IC (i.e., Integrated circuit with driver receiver or transceiver), IC package enclosure (e.g., Ball-Grid-Array, Flip-Chip, Quad Flat Package, etc.), Printed Circuit Board (PCB) with a connector interface to transmission media, and transmission media (e.g., copper or fiber optic cable).
The overall system throughput can be determined by the component with the narrowest bandwidth. Historically, the weakest link was the IC transceiver, due to the speed limitation of the silicon and gallium arsenide manufacturing technology. As the CMOS process pushes the speed envelope toward the 10 Gbps arena, other system components are subject to speed limiting hurdles. Package enclosures, mother boards and media interface connectors are becoming the performance limits for all systems above the 10 Gbps data transmission range.
Integrated circuits (IC's) typically constitute devices such as transistors and diodes and elements, such as resistors and capacitors, linked together by conductive connections to form one or more functional circuits. IC's are typically formed in a rectangular piece of silicon referred to as a “chip” or a “die”. Silicon dice can be formed in a wafer of silicon. A wafer is a sheet of silicon with a surface that is subject to a series of fabrication steps to form a pattern of identical IC's. The IC's are generally separated from each other by a repeating rectangular pattern of scribe lines, also called “saw” lines located in the surface of the wafer that serve as boundaries between the dice. A single IC can be formed in each die. At a late stage in a fabrication process, the dice are typically diced (i.e., cut apart) from the wafer along the scribe lines and each die is then bonded to a substrate to form an IC package.
Presently, the most popular IC package enclosure is the Ball-Grid-Array (BGA) package. The popularity of BGA arrangements is largely due to the large number of pins (e.g., exceeding 1,000 counts), small foot-print, low cost, reliability, and bandwidth adequate for present data rates well below 10 Gbps. Referring to FIG. 1, a pictorial view of a prior art BGA package 100 is illustrated, which is a popular surface mount chip package that utilizes a grid of solder balls 160 as its connectors. High-speed data signals enter the BGA package 100 through input ports 120 located on the left side of FIG. 1, by means of bondwires 110. IC transceivers are connected by bond wires 110 to the package posts 130. From the package posts 130, the signal flows through a package trace 170, a respective via 140 and then exits the package at the solder ball 160. The package traces 170 continue beyond the vias 140 toward the edge of the BGA package 100. These extended trace sections are known as “stubs”. Any signal trace shape change from the rectangular form and direction change from the straight line, can affect on trace characteristic impedance and attenuation.
The bondwires 110, with their circular cross-section, insert variability into the signal propagation (i.e., attenuation and reflection). The vias 140 add another discontinuity to the desired transmission line uniformity, with their self-resonance effect. And finally, the solder balls 160 represent still another non-uniform shape and self-resonance. All such discontinuities result in signal attenuation and reflections and destroy the signal integrity. Equally detrimental to the signal integrity is the cross-talk, which is due to undesirable signal coupling from the adjacent package traces 170. BGA crosstalk is primarily caused by bondwires 110 and package signal traces 170. Bondwires 110 and signal traces 170 lengths are comparable and cannot be further reduced to minimize the amount of crosstalk. The IC die size can cause additional variability of the wirebond lengths. The effects of the solder ball 160 and via 140 resonances can show up both in attenuation and the crosstalk frequency response.
Referring to FIG. 2, a prior art graphical representation of a crosstalk response 150 into signal trace 23 of BGA package 100 is illustrated. Signal trace 23 is the victim trace. From the aggressor traces 17 and 18, the crosstalk is generally −12 dB at 6 GHz as indicated in FIG. 2. It means that one fourth of the aggressor's transmitted signal with the third harmonic component of 6 GHz can appear in the adjacent signal trace 23. This precludes the use of BGA package for any data transmission systems with a data rate above 4 Gbps.
Referring to FIG. 3, another prior art graphical representation of a crosstalk performance 200 of BGA package 100 is illustrated. Here the crosstalk is generally in the range of −6 dB, as indicated in FIG. 3, meaning that one half of the aggressor's signal can be coupled into the victim package trace 170 as shown in FIG. 1. For a typical differential drive magnitude of 1 Vpk, the coupled crosstalk would be 500 mVpk. This is clearly unacceptable for all known data transmission standards.
Referring to FIG. 4, a pictorial view of a prior art Flip-Chip package 250 is illustrated. Flip Chip (FC) is not a specific package (such as SOIC), or even a package-type (like BGA) device. The term “Flip Chip” generally refers to the method of electrically connecting a die to a package carrier. In contrast, the interconnection between the die and carrier in flip chip packaging is configured through a conductive “bump” that is placed directly on the die surface. The FC package 250 depicted in FIG. 4 does not possess any bond wires, such as, for example, the bond wires 110 shown in FIG. 1. The FC package 250 is instead directly connected to an IC chip by means of solder bumps 410. The Flip-Chip package crosstalk is exemplified by signal traces 420. For high density Flip-Chip packages, the length of parallel trace coincidence can be excessive. Layout separation is sometimes difficult to achieve, and the advantage of the FC package 250 is lost in comparison with BGA package 100 described earlier. Solder bumps 410, solder balls 160 and vias 140 represent additional impedance mismatches in the transmission line, which can lead to signal reflections and further negative effects on the signal integrity.
Referring to FIG. 5, a prior art graphical representation of the crosstalk performance of FC package 250 depicted in FIG. 4 is illustrated. FC package 250 has an improved crosstalk performance in comparison to the BGA package 100 of approximately −18 dB. The solder bumps 410 solder balls 160 and vias 160 illustrated in FIG. 4 can cause local extremes in frequency responses. Their removal in new packages will further improve the attenuation and crosstalk performance.
In an effort to address the foregoing difficulties, a fissure can be added to the Flip-Chip type of package that significantly improves the crosstalk performance of the package for both high and low frequencies by 70 db and 32 dB respectively, up to 20 Gbps data rates. The fissure can be connected to any AC ground such as VSS or VDD package planes. The fissure can also accommodate the ingress of an optical fiber, which can allow the removal of the solder balls for high speed signal traces, with their respective vias. On-chip integrated LEDs or similar light source transceivers can drive the high speed signal media. Selective deposition of low dielectric material can improve the frequency response of high speed signal package traces.